|| You should have been through the entire ASIC design cycle (Verilog, Synopsys Design Compiler, Prime Time, BIST/SCAN insertion, RTL/gate level verification, Back End ASIC or COT model). IBM experience a plus. Should be proficient in RTL coding, synthesis, and microarchitecture design. Must be hands-on and have leadership experience. MS EE required. Ph.D. a plus.
|| This position requires 7+ years of ASIC experience with 3+ years of Networking ASIC experience.
|| You will be designing complex high speed ASICs for high performance products.You will contribute individually as well as lead a team of junior ASIC Design/Verification Engineers.
|| Location : Bay Area
Duration : Permanent
Apply with resume,Job Code in subject line and daytime telephone number.